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1 MEG x 16 FPM DRAM
FPM DRAM
FEATURES
* JEDEC- and industry-standard x16 timing, functions, pinouts, and packages * High-performance, low-power CMOS silicon-gate process * Single power supply (+3.3V 0.3V or 5V 0.5V) * All inputs, outputs and clocks are TTL-compatible * Refresh modes: RAS#-ONLY, CAS#-BEFORE-RAS# (CBR) and HIDDEN * Optional self refresh (S) for low-power data retention * BYTE WRITE and BYTE READ access cycles * 1,024-cycle refresh (10 row, 10 column addresses) * FAST-PAGE-MODE (FPM) access
MT4C1M16C3, MT4LC1M16C3
For the latest data sheet revisions, please refer to the Micron Web site: www.micron.com/datasheets
PIN ASSIGNMENT (Top View) 42-Pin SOJ
VCC DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 NC NC WE# RAS# NC NC A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 VSS DQ15 DQ14 DQ13 DQ12 VSS DQ11 DQ10 DQ9 DQ8 NC CASL# CASH# OE# A9 A8 A7 A6 A5 A4 VSS
VCC DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 NC
44/50-Pin TSOP
1 2 3 4 5 6 7 8 9 10 11 50 49 48 47 46 45 44 43 42 41 40 VSS DQ15 DQ14 DQ13 DQ12 VSS DQ11 DQ10 DQ9 DQ8 NC
OPTIONS
* Voltage 1 3.3V 5V * Packages Plastic SOJ (400 mil) Plastic TSOP (400 mil) * Timing 50ns access 60ns access * Refresh Rates Standard Refresh (16ms period) Self Refresh (128ms period) * Operating Temperature Range Commercial (0oC to +70oC) Extended (-20oC to +80oC)
Part Number Example:
MARKING
LC C
NC NC WE# RAS# NC NC A0 A1 A2 A3 VCC
15 16 17 18 19 20 21 22 23 24 25
36 35 34 33 32 31 30 29 28 27 26
NC CASL# CASH# OE# A9 A8 A7 A6 A5 A4 VSS
DJ TG -5 -6 None S2 None ET 3
NOTE: The # symbol indicates signal is active LOW.
1 MEG x 16 FPM DRAM PART NUMBERS
PART NUMBER MT4LC1M16C3DJ-6 MT4LC1M16C3DJ-6 S MT4LC1M16C3TG-6 MT4LC1M16C3TG-6 S MT4C1M16C3DJ-6 MT4C1M16C3TG-6 SUPPLY PACKAGE REFRESH 3.3V SOJ Standard 3.3V SOJ Self 3.3V TSOP Standard 3.3V TSOP Self 5V SOJ Standard 5V TSOP Standard
MT4LC1M16C3DJ-5
NOTE: 1. The third field distinguishes the low voltage offering: LC designates VCC = 3.3V and C designates VCC = 5V. 2. Contact factory for availability. 3. Available only on MT4C1M16C3 (5V)
GENERAL DESCRIPTION
The 1 Meg x 16 DRAM is a randomly accessed, solidstate memory containing 16,777,216 bits organized in a x16 configuration. The 1 Meg x 16 DRAM has both BYTE WRITE and WORD WRITE access cycles via two CAS# pins (CASL# and CASH#). These function identically to a single CAS# on other DRAMs in that either CASL# or CASH# will generate an internal CAS#. The CAS# function and timing are determined by the first CAS# (CASL# or CASH#) to transition LOW and
KEY TIMING PARAMETERS
SPEED -5 -6
tRC tRAC tPC tAA tCAC tRP
84ns 110ns
50ns 60ns
20ns 35ns
25ns 30ns
15ns 15ns
30ns 40ns
1 Meg x 16 FPM DRAM D51_5V_B.p65 - Rev. B; Pub 3/01
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc.
1 MEG x 16 FPM DRAM
GENERAL DESCRIPTION (continued)
the last CAS# to transition back HIGH. Use of only one of the two results in a BYTE access cycle. CASL# transitioning LOW selects an access cycle for the lower byte (DQ0-DQ7), and CASH# transitioning LOW selects an access cycle for the upper byte (DQ8-DQ15). Each bit is uniquely addressed through the 20 address bits during READ or WRITE cycles. These are entered ten bits (A0-A9) at a time. RAS# is used to latch the first ten bits and CAS# the latter ten bits. The CAS# function is determined by the first CAS# (CASL# or CASH#) to transition LOW and the last one to transition back HIGH. The CAS# function also determines whether the cycle will be a refresh cycle (RAS#-ONLY) or an active cycle (READ, WRITE, or READ-WRITE) once RAS# goes LOW. The CASL# and CASH# inputs internally generate a CAS# signal that functions identically to a single CAS# input on other DRAMs. The key difference is that each CAS# input (CASL# and CASH#) controls its corresponding DQ tristate logic (in conjunction with OE# and WE#). CASL# controls DQ0-DQ7 and CASH# controls DQ8-DQ15. The two CAS# controls give the 1 Meg x 16 DRAM BYTE WRITE cycle capabilities. A logic HIGH on WE# dictates read mode, while a logic LOW on WE# dictates write mode. During a WRITE cycle, data-in (D) is latched by the falling edge of WE# or CAS, whichever occurs last. Taking WE# LOW will initiate a WRITE cycle, selecting DQ0-DQ15. If WE# goes LOW prior to CAS# going LOW, the output pin(s) remain open (High-Z) until the next CAS# cycle. If WE# goes LOW after CAS# goes LOW and data reaches the output pins, data-out (Q) is activated and retains the selected cell data as long as CAS# and OE# remain LOW (regardless of WE# or RAS#). This late WE# pulse results in a READ-WRITE cycle. The 16 data inputs and 16 data outputs are routed through 16 pins using common I/O. Pin direction is controlled by OE# and WE#.
FUNCTIONAL BLOCK DIAGRAM
WE# CASL# CASH# DQ0 16 NO. 2 CLOCK GENERATOR DATA-OUT BUFFER
10
CAS#
DATA-IN BUFFER
DQ15
10 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 10
COLUMNADDRESS BUFFER REFRESH CONTROLLER
COLUMN DECODER
16
1,024
OE#
16
SENSE AMPLIFIERS I/O GATING REFRESH COUNTER 10
ROW DECODER
1,024 x 16
ROWADDRESS BUFFERS (10)
10
1,024
1,024 x 1,024 x 16 MEMORY ARRAY
RAS#
NO. 1 CLOCK GENERATOR
VDD VSS
1 Meg x 16 FPM DRAM D51_5V_B.p65 - Rev. B; Pub 3/01
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc.
1 MEG x 16 FPM DRAM
GENERAL DESCRIPTION (continued)
The MT4LC1M16C3 must be refreshed periodically in order to retain stored data. and executing anyRAS# cycle (READ, WRITE) or RAS# REFRESH cycle (RAS# ONLY, CBR or HIDDEN) so that all 1,024 combinations of RAS# addresses (A0-A9) are executed at least every 16ms (128ms on the "S" version), regardless of sequence. The CBR REFRESH cycle will also invoke the refresh counter and controller for row-address control.
FAST PAGE MODE ACCESS
FAST-PAGE-MODE operations allow faster data operations (READ, WRITE or READ-MODIFY-WRITE) within a row-address-defined (A0-A9) page boundary. The FAST-PAGE-MODE cycle is always initiated with a row address strobed in by RAS#, followed by a column address strobed in by CAS#. Additional columns may be accessed by providing valid column addresses, strobing CAS# and holding RAS# LOW, thus executing faster memory cycles. Returning RAS# HIGH terminates the FAST-PAGE-MODE operation. Returning RAS# and CAS# HIGH terminates a memory cycle and decreases chip current to a reduced standbylevel. The chip is also preconditioned for the next cycle during the RAS# HIGH time. Memory cell data is retained in its correct state by maintaining power
BYTE ACCESS CYCLE
The BYTE WRITEs and BYTE READs are determined by the use of CASL# and CASH#. Enabling CASL# will select a lower byte access (DQ0-DQ7), while enabling CASH# will select an upper byte access (DQ0-DQ15). Enabling both CASL# and CASH# selects a WORD WRITE cycle. The 1 Meg x 16 DRAM may be viewed as two 1 Meg x 8 DRAMs that have common input controls, with the exception of the CAS# inputs. Figure 1 illustrates the BYTE WRITE and WORD WRITE cycles. Figure 2 illustrates BYTE READ and WORD READ cycles.
WORD WRITE
LOWER BYTE WRITE
RAS#
CASL#
CASH#
WE#
STORED DATA 1 1
INPUT DATA 0 0 1 0 0 0 0 0
INPUT DATA
STORED DATA 0 0 1 0 0 0 0 0
STORED DATA 0 0 1 0 0 0 0 0
LOWER BYTE (DQ0-DQ7) OF WORD
0 1 1 1 1 1
INPUT DATA 1 1 0 1 1 1 1 1
INPUT DATA
STORED DATA 1 1 0 1 1 1 1 1
0
UPPER BYTE (DQ8-DQ15) OF WORD
1 0 1 0 0 0 0
X X X X X X X X
1 0 1 0 1 1 1 1
1 0 1 0 1 1 1 1
1 0 1 0 1 1 1 1
X X X X X X X X
1 0 1 0 1 1 1 1
ADDRESS 0
ADDRESS 1
X = NOT EFFECTIVE (DON'T CARE)
Figure 1 WORD and BYTE WRITE Example
1 Meg x 16 FPM DRAM D51_5V_B.p65 - Rev. B; Pub 3/01
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1 MEG x 16 FPM DRAM
Additionally, both bytes must always be of the same mode of operation if both bytes are active. A CAS# precharge must be satisfied prior to changing modes of operation between the upper and lower bytes. For example, an EARLY WRITE on one byte and a LATE WRITE on the other byte are not allowed during the same cycle. However, an EARLY WRITE on one byte and a LATE WRITE on the other byte, after a CAS# precharge has been satisfied, are permissible. the choice of a fully static, low-power data retention mode or a dynamic refresh mode at the extended refresh period of 128ms, or 125s per row, when using a distributed CBR REFRESH. This refresh rate can be applied during normal operation, as well as during a standby or battery backup mode. The self refresh mode is terminated by driving RAS# HIGH for a minimum time of tRPS. This delay allows for the completion of any internal refresh cycles that may be in process at the time of the RAS# LOWto-HIGH transition. If the DRAM controller uses a distributed CBR refresh sequence, a burst refresh is not required upon exiting self refresh. However, if the DRAM controller utilizes a RAS#-ONLY or burst CBR refresh sequence, all 1,024 rows must be refreshed using a minimum tRC refresh rate prior to resuming normal operation.
DRAM REFRESH
Preserve correct memory cell data by maintaining power and executing any RAS# cycle (READ, WRITE) or RAS# REFRESH cycle (RAS#-ONLY, CBR or HIDDEN) so that all 1,024 combinations of RAS# addresses are executed within tREF (MAX), regardless of sequence. The CBR and EXTENDED and SELF REFRESH cycles will invoke the internal refresh counter for automatic RAS# addressing. An optional self refresh mode is available on the "S" version. The self refresh feature is initiated by performing a CBR REFRESH cycle and holding RAS# LOW for the specified tRASS. The "S" option allows the user
STANDBY
Returning RAS# and CAS# HIGH terminates a memory cycle and decreases chip current to a reduced standby level. The chip is preconditioned for the next cycle during the RAS# HIGH time.
WORD READ RAS#
LOWER BYTE READ
CASL#
CASH#
WE#
STORED DATA
OUTPUT DATA 1 1 0 1 1 1 1 1 0 1 0 1 0 0 0 0
OUTPUT DATA 1 1 0 1 1 1 1 1 0 1 0 1 0 0 0 0
STORED DATA 1 1 0 1 1 1 1 1 0 1 0 1 0 0 0 0
STORED DATA 1 1 0 1 1 1 1 1 0 1 0 1 0 0 0 0
OUTPUT DATA 1 1 0 1 1 1 1 1 0 1 0 1 0 0 0 0
OUTPUT DATA 1 1 0 1 1 1 1 1 0 1 0 1 0 0 0 0
STORED DATA 1 1 0 1 1 1 1 1 0 1 0 1 0 0 0 0
LOWER BYTE (DQ0-DQ7) OF WORD
1 1 0 1 1 1 1 1 0
UPPER BYTE (DQ8-DQ15) OF WORD
1 0 1 0 0 0 0
ADDRESS 0 Z = High-Z
ADDRESS 1
Figure 2 WORD and BYTE READ Example
1 Meg x 16 FPM DRAM D51_5V_B.p65 - Rev. B; Pub 3/01
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc.
1 MEG x 16 FPM DRAM
ABSOLUTE MAXIMUM RATINGS*
Voltage on VCC Pin Relative to VSS 3.3V ..................................................... -1V to +4.6V 5V ........................................................... -1V TO +7V Voltage on NC, Inputs or I/O Pins Relative to VSS 3.3V ..................................................... -1V to +5.5V 5V ........................................................... -1V TO +7V Operating Temperature TA (commercial) ...................................... 0C to +70C TA (extended "ET") ............................ -20C to +80C Storage Temperature (plastic) ............ -55C to +150C Power Dissipation ........................................................ 1W *Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(Notes: 1, 5, 6; notes can be found on page 9); VCC (MIN) VCC VCC (MAX) 3.3V PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Valid Logic 1; All inputs, I/Os and any NC INPUT LOW VOLTAGE: Valid Logic 0; All inputs, I/Os and any NC INPUT LEAKAGE CURRENT: Any input at VIN (0V VIN VCC + 0.3V); All other pins not under test = 0V OUTPUT HIGH VOLTAGE: IOUT = -2mA OUTPUT LOW VOLTAGE: IOUT = 2mA OUTPUT LEAKAGE CURRENT: Any output at VOUT [0V VOUT VCC (MAX)]; DQ is disabled and in High-Z state SYMBOL VCC VIH VIL II MIN 3 2 -1.0 -2 MAX 3.6 5.5 0.8 2 MIN 4.5 2.4 -0.5 -2 5V MAX UNITS NOTES 5.5 VCC + 1 0.8 2 V V V A
VOH VOL IOZ
2.4 - -5
- 0.4 5
2.4 - -5
- 0.4 5
V V A
1 Meg x 16 FPM DRAM D51_5V_B.p65 - Rev. B; Pub 3/01
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc.
1 MEG x 16 FPM DRAM
ICC OPERATING CONDITIONS AND MAXIMUM LIMITS
(Notes: 1, 2, 3, 5, 6; notes can be found on page 9); VCC (MIN) VCC VCC (MAX) PARAMETER/CONDITION STANDBY CURRENT: TTL (RAS# = CAS# = VIH) STANDBY CURRENT: CMOS (non-"S" version only) (RAS# = CAS# = other inputs = VCC - 0.2V) STANDBY CURRENT: CMOS ("S" version only) (RAS# = CAS# = other inputs = VCC - 0.2V) OPERATING CURRENT: Random READ/WRITE Average power supply current (RAS#, CAS#, address cycling: tRC = tRC [MIN]) OPERATING CURRENT: FAST PAGE MODE Average power supply current (RAS# = VIL, CAS#, address cycling: tPC = tPC [MIN]) REFRESH CURRENT: RAS#-ONLY Average power supply current (RAS# cycling, CAS# = VIH: tRC = tRC [MIN]) REFRESH CURRENT: CBR Average power supply current (RAS#, CAS#, address cycling: tRC = tRC [MIN]) REFRESH CURRENT: Extended ("S" version only) Average power supply current: CAS# = 0.2V or CBR cycling; RAS# = tRAS (MIN); WE# = VCC - 0.2V; A0-A11, OE# and DIN = VCC - 0.2V or 0.2V (DIN may be left open) REFRESH CURRENT: Self ("S" version only) Average power supply current: CBR with RAS# tRASS (MIN) and CAS# held LOW; WE# = VCC - 0.2V; A0-A11, OE# and DIN = VCC - 0.2V or 0.2V (DIN may be left open) SYMBOL SPEED 3.3V ICC1 ICC2 ICC2 ALL ALL ALL -5 -6 -5 -6 -5 -6 -5 -6 1 500 150 180 170 110 90 180 170 180 170 5V 2 500 150 190 180 120 110 190 180 180 180 UNITS NOTES mA A A
ICC3
mA
23
ICC4
mA
23
ICC5
mA
ICC6
mA
4, 7
ICC7
ALL
300
300
A
4, 7
ICC8
ALL
300
300
A
4, 7
CAPACITANCE
(Note: 2; notes can be found on page 9); PARAMETER Input Capacitance: Addresses Input Capacitance: RAS#, CASL#, CASH#, WE#, OE# Input/Output Capacitance: DQ SYMBOL MAX UNITS CI1 CI2 CIO 5 7 7 pF pF pF
1 Meg x 16 FPM DRAM D51_5V_B.p65 - Rev. B; Pub 3/01
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1 MEG x 16 FPM DRAM
AC ELECTRICAL CHARACTERISTICS
(Notes: 5, 6, 7, 8, 9, 10, 11, 12; notes can be found on page 9); VCC (MIN) VCC VCC (MAX)
AC CHARACTERISTICS PARAMETER Access time from column address Column-address hold time (referenced to RAS#) Column-address setup time Row-address setup time Column address to WE# delay time Access time from CAS Column-address hold time CAS# pulse width CAS# LOW to "Don't Care" during Self Refresh CAS# hold time (CBR Refresh) Last CAS# going LOW to first CAS# to return HIGH CAS# to output in Low-Z CAS# precharge time Access time from CAS# precharge CAS# to RAS# precharge time CAS# hold time CAS# setup time (CBR Refresh) CAS# to WE# delay time WRITE command to CAS# lead time Data-in hold time Data-in setup time Output disable Output enable OE# hold time from WE# during READ-MODIFY-WRITE cycle Output buffer turn-off delay OE# setup prior to RAS# during HIDDEN Refresh cycle FAST-PAGE-MODE READ or WRITE cycle time FAST-PAGE-MODE READ-WRITE cycle time Access time from RAS# RAS# to column-address delay time Row-address hold time RAS# pulse width RAS# pulse width (FAST PAGE MODE) RAS# pulse width (Self Refresh) Random READ or WRITE cycle time RAS# to CAS# delay time READ command hold time (referenced to CAS) READ command setup time Refresh period (1,024 cycles) Refresh period (1,024 cycles) "S" version RAS# precharge time RAS# to CAS# precharge time RAS# precharge time (Self Refresh) READ command hold time (referenced to RAS#) RAS# hold time READ-WRITE cycle time -5 SYMBOL tAA tAR tASC tASR tAWD tCAC tCAH tCAS tCHD tCHR tCLCH tCLZ tCP tCPA tCRP tCSH tCSR tCWD tCWL tDH tDS tOD tOE tOEH
tOFF tORD tPC tPRWC tRAC tRAD tRAH tRAS tRASP tRASS tRC tRCD tRCH tRCS tREF tREF tRP tRPC tRPS tRRH tRSH tRWC
-6 MAX 25 MIN 45 0 0 49 15 15 10 10 15 10 10 0 5 5 45 5 35 10 10 0 0 10 12 0 0 25 56 12 10 60 60 100 104 14 0 0 15 10,000 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s ns ns ns ns ms ms ns ns ns ns ns ns NOTES
MIN 38 0 0 42 8 8 15 8 10 0 8 5 38 5 28 8 8 0 0 8 0 0 20 47 9 9 50 50 100 84 11 0 0
27 18 29 27 32, 35 4, 28 30 26, 29 30 28 28 28 4, 27 18, 27 23, 29 19, 29 19, 29 17, 26, 29 22 20 11, 17, 23 31 31 20
10,000
28
35
12 12
15 15
50
60
10,000 125,000
10,000 125,000
14, 27 16, 28 27
16 128 30 5 90 0 13 116 40 5 105 0 15 140
16 128
16 36
1 Meg x 16 FPM DRAM D51_5V_B.p65 - Rev. B; Pub 3/01
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc.
1 MEG x 16 FPM DRAM
AC ELECTRICAL CHARACTERISTICS
(Notes: 5, 6, 7, 8, 9, 10, 11, 12; notes can be found on page 9); VCC (MIN) VCC VCC (MAX)
AC CHARACTERISTICS PARAMETER RAS# to WE# delay time WRITE command to RAS# lead time Transition time (rise or fall) WRITE command hold time WRITE command hold time (referenced to RAS#) WE# command setup time WRITE command pulse width WE# hold time (CBR Refresh) WE# setup time (CBR Refresh) -5 SYMBOL tRWD tRWL tT tWCH tWCR tWCS tWP tWRH tWRP MIN 67 13 2 8 38 0 5 8 8 MAX MIN 79 15 2 10 45 0 5 10 10 -6 MAX UNITS ns ns ns ns ns ns ns ns ns NOTES 18
50
50
36 18, 27
1 Meg x 16 FPM DRAM D51_5V_B.p65 - Rev. B; Pub 3/01
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1 MEG x 16 FPM DRAM
NOTES
1. 2. 3. All voltages referenced to VSS. This parameter is sampled. VCC = +3.3V or 5.0V; f = 1 MHz. ICC is dependent on output loading. Specified values are obtained with minimum cycle time and the output open. Enables on-chip refresh and address counters. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (0C TA 70C) for commercial and (-20C TA 80C) for extended "ET" is ensured. An initial pause of 100s is required after powerup, followed by eight RAS# refresh cycles (RAS#ONLY or CBR), before proper device operation is ensured. The eight RAS# cycle wake-ups should be repeated any time the tREF refresh requirement is exceeded. AC characteristics assume tT = 5ns. VIH (MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL (or between VIL and VIH). In addition to meeting the transition rate specification, all input signals must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. If CAS# = VIH, data output is High-Z. If CAS# = VIL, data output may contain data from the last valid READ cycle. Measured with a load equivalent to two TTL gates, 100pF and VOL = 0.8V and VOH = 2V. If CAS# is LOW at the falling edge of RAS#, Q will be maintained from the previous cycle. To initiate a new cycle and clear the Q buffer, CAS# must be pulsed HIGH for tCP. The tRCD (MAX) limit is no longer specified. tRCD (MAX) was specified as a reference point only. If tRCD was greater than the specified tRCD (MAX) limit, then access time was controlled exclusively by tCAC (tRAC [MIN] no longer applied). With or without the tRCD limit, tAA and tCAC must always be met. The tRAD (MAX) limit is no longer specified. tRAD (MAX) was specified as a reference point only. If tRAD was greater than the specified tRAD (MAX) limit, then access time was controlled exclusively by tAA (tRAC and tCAC no longer applied). With or without the tRAD (MAX) limit, tAA, tRAC, and tCAC must always be met. Either tRCH or tRRH must be satisfied for a READ cycle. 17. tOFF (MAX) defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. 18. tWCS, tRWD, tAWD, and tCWD are restrictive operating parameters in LATE WRITE and READMODIFY-WRITE cycles only. If tWCS tWCS (MIN), the cycle is an EARLY WRITE cycle and the data out-put will remain an open circuit throughout the entire cycle. If tRWD tRWD (MIN), tAWD tAWD (MIN) and tCWD tCWD (MIN), the cycle is a READ WRITE and the data output will contain data read from the selected cell. If neither of the above conditions is met, the state of Q (at access time and until CAS# or OE# goes back to VIH) is indeterminate. OE# held HIGH and WE# taken LOW after CAS# goes LOW result in a LATE WRITE (OE#-controlled) cycle. 19. These parameters are referenced to CAS# leading edge in EARLY WRITE cycles and WE# leading edge in LATE WRITE or READ-MODIFY-WRITE cycles. 20. During a READ cycle, if OE# is LOW then taken HIGH before CAS# goes HIGH, Q goes open. If OE# is tied permanently LOW, LATE WRITE and READ-MODIFY-WRITE operations are not permissible and should not be attempted. 21. A HIDDEN REFRESH may also be performed after a WRITE cycle. In this case, WE# = LOW and OE# = HIGH. 22. All other inputs at 0.2V or VCC - 0.2V. 23. Column address changed once each cycle. 24. LATE WRITE and READ-MODIFY-WRITE cycles must have both tOD and tOEH met (OE# HIGH during WRITE cycle) in order to ensure that the output buffers will be open during the WRITE cycle. The DQs will provide the previously read data if CAS# remains LOW and OE# is taken back LOW after tOEH is met. If CAS# goes HIGH prior to OE# going back LOW, the DQs will remain open. 25. The DQs open during READ cycles once tOD or tOFF occur. 26. The 3ns minimum is a parameter guaranteed by design. 27. The first CASx edge to transition LOW. 28. The last CASx edge to transition HIGH. 29. Output parameter (DQx) is referenced to corresponding CAS# input; DQ0-DQ7 by CASL# and DQ8-DQ15 by CASH#. 30. Last falling CASx edge to first rising CASx edge. 31. Last rising CASx edge to next cycle's last rising CASx edge.
4. 5.
6.
7. 8.
9.
10. 11. 12. 13.
14.
15.
16.
1 Meg x 16 FPM DRAM D51_5V_B.p65 - Rev. B; Pub 3/01
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1 MEG x 16 FPM DRAM
NOTES (continued)
32. 33. 34. 35. 36. Last rising CASx edge to first falling CASx edge. First DQs controlled by the first CASx to go LOW. Last DQs controlled by the last CASx to go HIGH. Each CASx must meet minimum pulse width. Last CASx to go LOW. 37. All DQs controlled, regardless CASL# and CASH#. 38. If OE# is tied permanently LOW, LATE WRITE, or READ-MODIFY-WRITE operations are not permissible and should not be attempted.
1 Meg x 16 FPM DRAM D51_5V_B.p65 - Rev. B; Pub 3/01
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc.
1 MEG x 16 FPM DRAM
READ CYCLE
tRC tRAS V IH V IL tCSH tRSH tCRP CASL#/CASH# V IH V IL tAR tASR V IH V IL tRAD tRAH tASC tCAH tRCD tCAS tCLCH tRRH tRP
RAS#
ADDR
ROW tRCS
COLUMN tRCH
ROW
WE#
V IH V IL tAA tRAC tCAC tCLZ tOFF
V DQ V IOH IOL
OPEN t OE
VALID DATA t OD
OPEN
OE#
V IH V IL
DON'T CARE UNDEFINED
TIMING PARAMETERS
-5 SYMBOL
tAA tAR tASC tASR tCAC tCAH tCAS tCLCH tCLZ tCRP tCSH tOD tOE
-6 MAX 25 MIN 45 0 0 15 15 10 10 10 0 5 12 12 45 0 15 15 10,000 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL
tOFF tRAC tRAD tRAH tRAS tRC tRCD tRCH tRCS tRP tRRH tRSH
-5 MIN 0 9 9 50 84 11 0 0 30 0 13 MAX 12 50 MIN 0 12 10 60 104 14 0 0 40 0 15
-6 MAX 15 60 UNITS ns ns ns ns ns ns ns ns ns ns ns ns
MIN 38 0 0 8 8 10 0 5 38 0
10,000
10,000
10,000
1 Meg x 16 FPM DRAM D51_5V_B.p65 - Rev. B; Pub 3/01
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1 MEG x 16 FPM DRAM
EARLY WRITE CYCLE
tRC tRAS V IH V IL tCSH tRSH tCRP CASL#/CASH# V IH V IL tAR tRAD tASR ADDR V IH V IL tRAH tASC tCAH tRCD tCAS tCLCH tRP
RAS#
ROW
COLUMN tCWL tRWL tWCS tWCR tWCH tWP
ROW
WE#
V IH V IL tDS tDH
V DQ V IOH IOL V IH V IL
VALID DATA
OE#
DON'T CARE UNDEFINED
TIMING PARAMETERS
-5 SYMBOL tAR tASC
tASR tCAH tCAS tCLCH tCRP tCSH tCWL tDH tDS tRAD
-6 MAX MIN 45 0 0 10 10,000 10 10 5 45 10 10 0 12 10,000 MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL tRAH tRAS
tRC tRCD tRP tRSH tRWL tWCH tWCR tWCS tWP
-5 MIN 9 50 84 11 30 13 13 8 38 0 5 MAX 10,000 MIN 10 60 104 14 40 15 15 10 45 0 5
-6 MAX 10,000 UNITS ns ns ns ns ns ns ns ns ns ns ns
MIN 38 0 0 8 8 10 5 38 8 8 0 9
1 Meg x 16 FPM DRAM D51_5V_B.p65 - Rev. B; Pub 3/01
12
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc.
1 MEG x 16 FPM DRAM
READ-WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE cycles)
tRWC tRAS V IH V IL tCSH tRSH tCAS tRP
RAS#
tCRP CASL#/CASH# V IH V IL tAR tRAD tRAH
tRCD
tCLCH
tASR ADDR V IH V IL
tASC
tCAH
ROW
COLUMN tRWD tCWD tAWD tCWL tRWL tWP
ROW
tRCS
WE#
V IH V IL tAA tRAC tCAC tCLZ tDS VALID D OUT tOE V IH V IL tOD tDH
V DQ V IOH IOL
OPEN
VALID D IN tOEH
OPEN
OE#
DON'T CARE UNDEFINED
TIMING PARAMETERS
-5 SYMBOL tAA tAR tASC
tASR tAWD tCAC tCAH tCAS tCLCH tCLZ tCRP tCSH tCWD tCWL tDH tDS
-6 MAX 25 MIN 45 0 0 49 15 15 10 10 10 0 5 45 35 10 10 0 10,000 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL
tOD tOE tOEH tRAC tRAD tRAH tRAS tRCD tRCS tRP tRSH tRWC tRWD tRWL tWP
-5 MIN 0 8 50 9 9 50 11 0 30 13 116 67 13 5 10,000 12 10 60 14 0 40 15 140 79 15 5 MAX 12 12 MIN 0 10
-6 MAX 15 15 60 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
MIN 38 0 0 42 8 8 10 0 5 38 28 8 8 0
10,000
10,000
1 Meg x 16 FPM DRAM D51_5V_B.p65 - Rev. B; Pub 3/01
13
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc.
1 MEG x 16 FPM DRAM
FAST-PAGE-MODE READ CYCLE
tRASP V IH V IL tCSH tCRP CASL#/CASH# V IH V IL tAR tASR ADDR V IH V IL tRAD tRAH tASC tCAH tASC tCAH tASC tCAH tRCD tCAS, tCLCH tPC tCP tCAS, tCLCH tCP tRSH tCAS, tCLCH tCP tRP
RAS#
ROW
COLUMN
COLUMN tRCS tRCH
COLUMN tRCS
ROW tRRH
tRCS WE# V IH V IL
tRCH
tRCH
tAA tRAC tCAC tCLZ DQ V IOH V IOL OPEN tOE V IH V IL VALID DATA tOD tOFF tCLZ
tAA tCPA tCAC tOFF tCLZ VALID DATA tOD
tAA tCPA tCAC tOFF
tOE
tOE
VALID DATA tOD
OPEN
OE#
DON'T CARE UNDEFINED
TIMING PARAMETERS
-5 SYMBOL tAA tAR
tASC tASR tCAC tCAH tCAS tCLCH tCLZ tCP tCPA tCRP tCSH tOD
-6 MAX 25 MIN 45 0 0 15 15 10 10,000 10 10 0 5 28 35 5 45 12 0 15 10,000 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL
tOE tOFF tPC tRAC tRAD tRAH tRASP tRCD tRCH tRCS tRP tRRH tRSH
-5 MIN 0 20 50 9 9 50 11 0 0 30 0 13 125,000 12 10 60 14 0 0 40 0 15 MAX 12 12 MIN 0 25
-6 MAX 15 15 60 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns
MIN 38 0 0 8 8 10 0 8 5 38 0
125,000
1 Meg x 16 FPM DRAM D51_5V_B.p65 - Rev. B; Pub 3/01
14
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc.
1 MEG x 16 FPM DRAM
FAST-PAGE-MODE EARLY WRITE CYCLE
tRASP V IH V IL tCSH tCRP CASL#/CASH# V IH V IL tAR tRAD tASR ADDR V IH V IL tRAH tASC tCAH tASC tCAH tASC tCAH tRCD tCAS, tCLCH tPC tCP tCAS, tCLCH tCP tRSH tCAS, tCLCH tCP tRP
RAS#
ROW
COLUMN tCWL tWCH tWP
COLUMN tCWL tWCH tWP
COLUMN tCWL tWCH tWP
ROW
tWCS
tWCS
tWCS
WE#
V IH V IL tWCR tDS tDH tDS tDH tDS tRWL tDH
V DQ V IOH IOL
VALID DATA
VALID DATA
VALID DATA
OE#
V IH V IL
DON'T CARE UNDEFINED
TIMING PARAMETERS
-5 SYMBOL tAR
tASC tASR tCAH tCAS tCLCH tCP tCRP tCSH tCWL tDH tDS
-6 MAX MIN 45 0 0 10,000 10 10 10 5 5 45 10 10 0 10,000 MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL
tPC tRAD tRAH tRASP tRCD tRP tRSH tRWL tWCH tWCR tWCS tWP
-5 MIN 20 9 9 50 11 30 13 13 8 38 0 5 125,000 MAX MIN 25 12 10 60 14 40 15 15 10 45 0 5
-6 MAX UNITS ns ns ns 125,000 ns ns ns ns ns ns ns ns ns
MIN 38 0 0 8 8 10 8 5 38 8 8 0
1 Meg x 16 FPM DRAM D51_5V_B.p65 - Rev. B; Pub 3/01
15
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc.
1 MEG x 16 FPM DRAM
FAST-PAGE-MODE READ-WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE cycles)
tRASP V IH V IL tCSH tCRP CASL#/CASH# V IH V IL tAR tRAD tRAH tRCD tCAS, tCLCH NOTE 1 tCP tPC tPRWC tCP tRSH tCAS, tCLCH tCP tCAS, tCLCH tRP
RAS#
tASR ADDR V IH V IL
tASC
tCAH
tASC
tCAH
tASC
tCAH
ROW
COLUMN tRWD tRCS tCWL tWP tAWD tCWD
COLUMN
COLUMN tRWL
ROW
tCWL tWP tAWD tCWD
tAWD tCWD
tCWL tWP
WE#
V IH V IL tAA tRAC tDH tDS tCAC tCLZ tAA tCPA tCAC tCLZ VALID VALID D OUT D IN tOD tOE tOE VALID VALID D OUT D IN tOD tOE tDH tDS tAA tCPA tCAC tCLZ VALID VALID D OUT D IN tOD OEH OPEN tDH tDS
DQ
V IOH V IOL
OPEN
OE#
V IH V IL
DON'T CARE UNDEFINED
TIMING PARAMETERS
-5 SYMBOL tAA tAR
tASC tASR tAWD tCAC tCAH tCAS tCLCH tCLZ tCP tCPA tCRP tCSH tCWD tCWL tDH
-6 MAX 25 MIN 45 0 0 49 15 15 10 10,000 10 10 0 5 28 35 5 45 35 10 10 10,000 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL tDS tOD
tOE tOEH tPC tPRWC tRAC tRAD tRAH tRASP tRCD tRCS tRP tRSH tRWD tRWL tWP
-5 MIN 0 0 8 20 47 50 9 9 50 11 0 30 13 67 13 5 125,000 12 10 60 14 0 40 15 79 15 5 MAX 12 12 10 25 56 MIN 0 0
-6 MAX 15 15 UNITS ns ns ns ns ns ns ns ns ns 125,000 ns ns ns ns ns ns ns ns
MIN 38 0 0 42 8 8 10 0 8 5 38 28 8 8
60
NOTE: 1. tPC is for LATE WRITE only.
1 Meg x 16 FPM DRAM D51_5V_B.p65 - Rev. B; Pub 3/01
16
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc.
1 MEG x 16 FPM DRAM
FAST-PAGE-MODE READ EARLY WRITE CYCLE (Pseudo READ-MODIFY-WRITE)
tRASP RAS# V IH V IL tRSH tCSH tCRP CASL#/CASH# V IH V IL tAR tRAD tASR ADDR V IH V IL tRAH tASC tCAH tASC tCAH tRCD tCAS tCP tPC tCAS tCP tRP
ROW
COLUMN
COLUMN tCWL tRWL tWCS tWP tWCH
ROW
tRCS
WE#
V IH V IL
tCAC t CLZ
NOTE 1 t OFF tDS VALID DATA
tDH
Q
V OH V OL
OPEN tAA tRAC
VALID DATA
OE#
V IH V IL
DON'T CARE UNDEFINED
TIMING PARAMETERS
-5 SYMBOL tAA
tAR tASC tASR tCAC tCAH tCAS tCLZ tCP tCRP tCSH tCWL tDH tDS
-6 MAX 25 MIN 45 0 0 15 15 10 10,000 10 0 5 5 45 10 10 0 10,000 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL
tOFF tPC tRAC tRAD tRAH tRASP tRCD tRCS tRP tRSH tRWL tWCH tWCS tWP
-5 MIN 0 20 50 9 9 50 11 0 30 13 13 8 0 5 125,000 12 10 60 14 0 40 15 15 10 0 5 MAX 12 MIN 0 25
-6 MAX 15 60 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns
MIN 38 0 0 8 8 0 8 5 38 8 8 0
125,000
NOTE: 1. tPC is for LATE WRITE only.
1 Meg x 16 FPM DRAM D51_5V_B.p65 - Rev. B; Pub 3/01
17
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc.
1 MEG x 16 FPM DRAM
RAS#-ONLY REFRESH CYCLE (OE# and WE# = DON'T CARE)
tRC tRAS V IH V IL tCRP V IH V IL tASR ADDR V IH V IL tRAH tRPC tRP
RAS#
CASL#/CASH#
ROW
ROW
V Q V OH OL
OPEN
CBR REFRESH CYCLE (Addresses and OE# = DON'T CARE)
tRP RAS# V IH V IL tRPC tCP CASL#/CASH# V IH V IL V OH V OL tWRP WE# V IH V IL tWRH OPEN tWRP tWRH tCSR tCHR tRPC tCSR tCHR tRAS NOTE 1 tRP tRAS
DQ
DON'T CARE UNDEFINED
TIMING PARAMETERS
-5 SYMBOL tASR tCHR
tCP tCRP tCSR tRAH
-6 MAX MIN 0 10 5 5 5 10 MAX UNITS ns ns ns ns ns ns SYMBOL
tRAS tRC tRP tRPC tWRH tWRP
-5 MIN 50 84 30 5 8 8 MAX MIN 60 104 40 5 10 10
-6 MAX 10,000 UNITS ns ns ns ns ns ns
MIN 0 8 8 5 5 9
NOTE: 1. End of CBR REFRESH cycle.
1 Meg x 16 FPM DRAM D51_5V_B.p65 - Rev. B; Pub 3/01
18
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc.
1 MEG x 16 FPM DRAM
HIDDEN REFRESH CYCLE 1 (WE# = HIGH; OE# = LOW)
tRAS RAS# V IH V IL tCRP V IH V IL tAR tRAD tASR V IH V IL tRAH tASC tCAH tRCD tRSH tCHR tRP tRAS
CASL#/CASH#
ADDR
ROW
COLUMN tAA tRAC tCAC tCLZ tOFF
V DQx V IOH IOL
OPEN t OE t ORD
VALID DATA tOD
OPEN
OE#
V IH V IL
DON'T CARE UNDEFINED
TIMING PARAMETERS
-5 SYMBOL tAA
tAR tASC tASR tCAC tCAH tCHR tCLZ tCRP tOD
-6 MAX 25 MIN 45 0 0 15 15 10 10 0 5 0 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns SYMBOL tOE
tOFF tORD tRAC tRAD tRAH tRAS tRCD tRP tRSH
-5 MIN 0 0 9 9 50 11 30 13 10,000 MAX 12 12 50 12 10 60 14 40 15 MIN 0 0
-6 MAX 15 15 60 UNITS ns ns ns ns ns ns ns ns ns ns
MIN 38 0 0 8 8 0 5 0
10,000
12
15
NOTE: 1. A HIDDEN REFRESH may also be performed after a WRITE cycle. In this case, WE# is LOW and OE# is HIGH.
1 Meg x 16 FPM DRAM D51_5V_B.p65 - Rev. B; Pub 3/01
19
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc.
1 MEG x 16 FPM DRAM
SELF REFRESH CYCLE (Addresses and OE# = DON'T CARE)
tRP V IH V IL tRASS NOTE 1 (( )) (( )) tCSR tCHD (( )) (( )) (( )) tWRP tWRH (( )) (( )) OPEN tWRP tWRH tRPS NOTE 2
RAS#
tRPC tCP
tRPC tCP
(( ))
CAS#
V IH V IL
V DQ V OH OL V WE# V IH IL
DON'T CARE UNDEFINED
TIMING PARAMETERS
-5 SYMBOL tCHD tCLCH tCP tCSR tRASS MIN 15 10 8 5 100 MAX MIN 15 10 5 5 100 -6 MAX UNITS ns ns ns ns s SYMBOL tRP tRPC tRPS tWRH tWRP MIN 30 5 90 8 8 -5 MAX MIN 40 5 105 10 10 -6 MAX UNITS ns ns ns ns ns
NOTE: 1. Once tRASS (MIN) is met and RAS# remains LOW, the DRAM will enter self refresh mode. 2. Once tRPS is satisfied, a complete burst of all rows should be executed if RAS#-only or burst CBR refresh is used.
1 Meg x 16 FPM DRAM D51_5V_B.p65 - Rev. B; Pub 3/01
20
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc.
1 MEG x 16 FPM DRAM
42-PIN PLASTIC SOJ (400 mil)
1.079 (27.41) 1.073 (27.25)
.405 (10.29) .399 (10.13) .445 (11.30) .435 (11.05)
PIN #1 INDEX
.050 (1.27) TYP 1.000 (25.40)
.032 (0.81) .026 (0.66)
.148 (3.76) .138 (3.51)
.095 (2.40) .080 (2.02)
SEATING PLANE
.037 (0.94) MAX DAMBAR PROTRUSION
.020 (0.51) .015 (0.38)
.380 (9.65) .360 (9.14)
.030 (0.76) MIN
NOTE:
1. All dimensions in inches (millimeters) MAX or typical where noted. MIN 2. Package width and length do not include mold protrusion; allowable mold protrusion is .01" per side.
1 Meg x 16 FPM DRAM D51_5V_B.p65 - Rev. B; Pub 3/01
21
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc.
1 MEG x 16 FPM DRAM
44/50-PIN PLASTIC TSOP (400 mil)
.828 (21.04) .822 (20.88) 50
SEE DETAIL A
.029 (0.75) TYP
.467 (11.86) .459 (11.66) .402 (10.21) .398 (10.11)
1 PIN #1 INDEX .031 (0.80) TYP .018 (0.45) .012 (0.30)
25
.007 (0.18) .005 (0.13)
.004 (0.10) .047 (1.20) MAX
.010 (0.25)
SEATING PLANE
.008 (0.20) .002 (0.05) DETAIL A .032 (0.80) TYP .024 (0.60) .016 (0.40)
NOTE:
1. All dimensions in inches (millimeters) MAX or typical where noted. MIN 2. Package width and length do not include mold protrusion; allowable mold protrusion is .01" per side.
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron is a registered trademark and the Micron logo and M logo are trademarks of Micron Technology, Inc.
1 Meg x 16 FPM DRAM D51_5V_B.p65 - Rev. B; Pub 3/01
22
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc.

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